标签：#pcb

Why HDI PCB Manufacturing Starts Long Before the First Hole Is Drilled When people think about PCB manufacturing, they usually imagine drilling, plating, imaging, etching, solder mask, and surface finishing. For conventional PCBs, that assumption isn't too far from reality. For HDI (High Density Interconnect) PCBs, however, manufacturing actually begins long before any physical production starts. The success of an HDI project is often determined during engineering review rather than on the factory floor. Manufacturing Starts with Design Decisions A PCB layout may pass every design rule check inside CAD software while still being difficult to manufacture efficiently. Typical examples include: unnecessary stacked microvias excessive sequential lamination extremely aggressive trace and space dimensions unrealistic copper balancing inefficient stack-up planning None of these issues are fabrication defects. They are engineering decisions. The earlier they are identified, the lower the overall project cost becomes. The Stack-Up Is More Important Than Many Engineers Expect One of the biggest misconceptions is that increasing the layer count automatically solves routing problems. In reality, a carefully planned stack-up usually provides greater benefits than simply adding more copper layers. A good stack-up improves: signal integrity impedance consistency EMI performance power distribution thermal behavior More importantly, it creates a PCB that is easier to manufacture repeatedly with stable quality. HDI Is a Balance Between Performance and Manufacturability Many first-time HDI designs focus only on routing density. Experienced engineers usually focus on manufacturability. For example: Should this microvia really be stacked? Can staggered vias achieve the same result? Is another lamination cycle actually necessary? Can the BGA fan-out be optimized differently? Each decision influences fabrication complexity, yield, lead time, and production cost. Why DFM Matters More for H

If you've submitted a BOM for quoting recently and gotten a lead time that made you do a double take, you're not imagining things. Passive component sourcing in 2026 is tighter than it's been in a few years — and MLCCs are the epicenter. I want to break down why this is happening, which component categories are actually at risk, and — more importantly — what you can do at the design stage to make your board less vulnerable to it. This isn't a "just wait it out" post; there are concrete layout and BOM decisions that meaningfully change your exposure. Why now? Three demand sources are converging on the same MLCC/inductor capacity that used to be dominated by consumer electronics: AI server infrastructure — GPU power delivery networks alone can chew through hundreds of decoupling capacitors per board, and hyperscaler order volumes dwarf typical consumer runs. EVs — automotive-grade passives (AEC-Q200, X8R/X7R) come from a narrower qualified supplier base, so even modest EV growth disproportionately tightens that segment. Renewables/grid infrastructure — pulling on high-voltage inductors and power resistors. On the supply side, new MLCC/ferrite production lines take 12–24 months to come online from the capital decision. Semiconductor fabs can reallocate capacity relatively fast; passive component fabs can't. That structural lag is the real reason lead times stretch out faster than they recover. Which parts are actually at risk Not everything is equally exposed: Category Normal LT 2026 Tight-Market LT Exposure Commercial MLCC (X7R, 0402/0603) 4–8 wks 8–16 wks Moderate–High High-density MLCC (0201, high µF) 6–10 wks 16–26 wks High Automotive MLCC (AEC-Q200, X8R) 10–14 wks 20–30+ wks Very High C0G/NP0 (precision/timing) 4–8 wks 6–12 wks Low–Moderate Power inductors (shielded, low DCR) 6–10 wks 12–20 wks Moderate–High Chip resistors 2–6 wks 4–8 wks Low Chip resistors are the least affected — manufacturing capacity is less concentrated and swapping vendors doesn't trigger a

Intel Foundry's Rio Rancho Facility Moves Toward Glass Substrate Volume Production Reports from Wccftech and Forbes (May 26, 2026) indicate that Intel Foundry's facility in Rio Rancho, New Mexico, is advancing toward becoming the world's first factory to achieve mass production of glass substrates — a next-generation chip packaging technology considered critical for scaling AI hardware beyond current organic substrate limitations. The facility has already begun manufacturing silicon photonics products for external customers and is expected to play a central role in Intel's advanced packaging strategy. Why Glass Substrates Matter for AI Glass substrates address fundamental limitations of current organic (ABF) substrates that are becoming bottlenecks for AI chip scaling: Extreme flatness (<1 μm warpage) enables larger die and chiplet assemblies Low CTE (3-8 ppm/°C) closely matches silicon (2.6 ppm/°C), reducing thermal stress Higher interconnect density due to dimensional stability Better high-frequency performance with low dielectric loss Larger format supporting bigger interposers than organic substrates For AI accelerators that already push CoWoS substrate limits at 5,500+ mm², glass substrates could enable even larger multi-chiplet assemblies. Intel's Advanced Packaging Ecosystem Intel has been building an advanced packaging portfolio: EMIB (Embedded Multi-die Interconnect Bridge): High-density die-to-die connections Foveros : 3D stacking for logic-on-logic packaging Co-Packaged Optics (CPO) : Recently demonstrated glass-core substrate prototypes with CPO Customer Base According to Forbes: Existing customers : AWS, Cisco Reportedly in discussion : Apple, Google, Microsoft, Nvidia, Tesla Commercial Timeline Milestone Timeline Glass substrate R&D announcement 2023 Pilot line (Chandler, AZ) 2024-2025 Silicon photonics production (Rio Rancho) 2026 (active) Glass substrate volume production ~2028-2030 Global Competition Intensifying SKC/Absolics (Korea): Operating pilo

Lithium battery packs are only as strong as their weakest cell. Whether you're designing a drone battery, an EV pack, or an energy storage system, cell balancing plays a critical role in battery safety, lifespan, and performance. But many developers and hardware engineers still confuse passive balancing and active balancing , or underestimate how important balancing becomes in multi-cell lithium systems. In this article, we'll break down: Why battery balancing matters What causes cell imbalance How passive balancing works How active balancing works Engineering trade-offs between both methods Where each balancing strategy is commonly used 1. Why Battery Cells Become Unbalanced In theory, every lithium cell inside a battery pack should behave identically. In reality, that never happens. Even cells from the same production batch will have slight differences in: Internal resistance Capacity Self-discharge rate Temperature response Aging characteristics Over time, those small differences accumulate. For example: One cell may charge slightly faster Another may discharge deeper One may heat up more under load Eventually, the pack voltage becomes uneven. This is called cell imbalance . 2. Why Cell Imbalance Is Dangerous Imagine a 4S lithium battery pack. If one cell reaches 4.25V while the others are still at 4.10V, the charger must stop to avoid overcharging that single cell. That means: The entire pack never reaches full usable capacity Weak cells age faster Heat generation increases Safety risks become higher The same problem happens during discharge. If one cell drops below the minimum safe voltage earlier than others, the BMS cuts power to protect the pack — even though the remaining cells still contain energy. In other words: A battery pack is limited by its weakest cell. 3. What Is Battery Balancing? Battery balancing is the process of equalizing cell voltages inside a battery pack. The goal is simple: Prevent overcharge Prevent over-discharge Improve pack lifespan I